This design continues the current modular approach, but drops the DSPs. System design, schematics, and first-round programming were all done by
Brad Taylor.
A 'C' syntax HDL compiler producing .XNF files was designed by
Rob Dowling. As of 1996 a PCIbus card, the "G900", has been the preferred interface for these modules, with Xmods carrying XC4028s.
G800 detail - a view of the "XPGA" routing sitting under the first module. This FPGA supports the VESA Media Channel on the G800 "RIC" (reconfigurable interface card). The supported modules are 2.4" x 3.65", GigaOps' standard module size. 200 pins of reconfigurable high speed bus are supplied to each card position. Four cards can be stacked in each location, yielding 16 modules on the G800. This board has four signal layers, and eight matched-length clock lines. 78KB
X210MOD, rev A - This design is the first X210MOD fab. It features two XC4010s (or 4013s, or 4020s), bus switch isolation for each FPGA, memory which can be shared, 8MB DRAM and 256KB of SRAM, and two of uChip's PIC16C71 monitor CPUs for incoming file checking, and for temperature and current sensing. FPGAs are protected from possible user-induced over-current conditions. This is my PCB design; some of the routing was done by
W. A. Hill. 93KB
X210MOD, rev B - This design is the current XMOD fab. It has the same components and features as the rev A design. This revision of my earlier design was done by Viet Tran at Hytek Designs. The revision was to accomodate larger SOJ packages for the SRAM which were not available in TSOP at the time. I have since done a rev C, not shown here. 57KB
XMOD, mechanical - This drawing shows the standard mechanical features of a module. This drawing is made available to let other designers create a place for Gigaops modules in their systems. 33KB
Access to images of design work:
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